The present invention relates to a mask-programmable logic macro and a method for programming a logic macro.
The design of digital electronic circuits is characterized nowadays by a continual increase in the circuit complexity, a continuous drive toward miniaturization and severe time and cost pressure for the circuit users and manufacturers. In order to be able to react rapidly in the event of changing requirements made of digital circuits, so-called FPGA (field programmable gate arrays) have therefore been developed, which represent logic circuits which can be programmed by the user himself. FPGA have an array arrangement of programmable logic macros which can each perform logic functions. A complex logic chip with logic functions is then achieved by programming connections or the interconnection of the logic macros with one another.
The individual logic macros or logic cells are based essentially on arrangements of look-up tables which realize a Boolean function. A look-up table having N inputs should thus be able to realize 22N Boolean functions. In the case of three input signals, these are for example 256 possible Boolean functions. The flexibility of FPGA architectures by virtue of programmability that is possible “in the field” requires a complicated area-intensive connection system, configuration memory elements and an extensive wiring. As a result of which FPGA components have comparatively slow processing times and are additionally expensive to develop and procure.
So-called application specific integrated circuits (ASICs) represent a compromise between comparatively easy adaptability of their logic functions and high processing speed. ASICs that may be mentioned are in particular gate arrays containing a regular arrangement of digital basic elements which can be combined with one another by interconnections in the production process.
Structured ASICs are partly prefabricated and predefined electronic circuits which are converted into application specific logic circuits during the fabrication process by specially adapted masking steps, by way of example. The production process usually involves process-technologically setting switches for the definition of the signal paths within the ASIC, such as for example by vias or applied metal connections.
U.S. Pat. No. 6,285,218 B1 describes for example a method for producing programmable logic cell arrays in which logic cells are formed by means of standardized masks. What is disadvantageous in this case is primarily the fact that in production for forming an individual logic cell of this type, it is necessary to use a plurality of different masks for the required standard elements. Moreover, only a limited number of Boolean functions can be realized by means of the logic elements of U.S. Pat. No. 6,285,218 B1.
A logic macro that can be used flexibly should be able, however, to realize all possible Boolean functions given a predetermined number of input signals, that is to say 22N Boolean functions given N input signals. German patent 3148410 C2 discloses a programmable logic cell having three inputs, transistors connected in series essentially being arranged such that they are connected up in programmable fashion between a supply voltage and an output. Input signals are passed in each case to the control terminals of the transistors. A desired Boolean function is obtained by virtue of the fact that the controllable paths of the transistors can be bridged by further transistors in programmable fashion. The logic circuit in accordance with German patent 3148410 C2 also has the disadvantage that only a limited number of Boolean functions can be realized. Moreover, the programmability “in the field” requires a high outlay on circuitry which is manifested in a complicated production method comprising many processing steps. Consequently, the prior art also does not include any logic macros which can be adapted flexibly by a small number of programming steps specified in the production process.
There is a need, therefore, for a programmable logic device that addresses the shortcomings of the prior art.